It is well known that the impedance matrix equation obtained by discretizing the electric field integral equation (EFIE) is dense and ill-conditioned. In this paper, a combination of the Sherman-Morrison-Woodbury (SMW) formula-based preconditioner and the adaptive cross approximation (ACA) algorithm is proposed to accelerate the iterative solution of the EFIE. The SMW preconditioner (SMWP) and the ACA algorithm are employed to reduce the number of iterations and the complexity of a matrix-vector product (MVP), respectively. The SMWP can efficiently construct a sparse approximate inverse of the impedance matrix with the aid of the SMW formula. It can be considered as an improved version of the conventional block diagonal preconditioner (BDP) and has better performance. Numerical results are provided to demonstrate that the hybrid SMWP-ACA is effective to reduce the iterative solution time.

α-stable distribution is a kind of non-Gaussian signal, and it is more likely to exhibit sharp spikes or occasional bursts of outlying observations than one would expect from normally distributed signals. So it is difficult to accurately estimate the parameters of chirp signal in α-stable noise. In addressing this problem, a novel method of accurate parameter estimation of chirp signal is proposed. Firstly, the characteristics of α-stable noise are analysed. Secondly, the chirp signal in α-stable noise is transformed into Gaussian-like distribution. Then, fractional Fourier transform is used to calculate the parameters of the initial frequency and chirp rate. By simulation, the method is verified to be effective and rational. The proposed method can effectively estimate the initial frequency and chirp rate of the chirp signal in α-stable noise.

This paper presents a 200-Mb/s to 3.2-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180 nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking and reduce the frequency acquisition time. A frequency band selector for wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 11-ps peak-to-peak jitter at 3 Gb/s and the frequency acquisition time of 11.8 µs.

A 60-GHz 2 × 2 corporate-fed patch antenna array based on surface micromachined micro-coaxial technology is presented in this paper. The low loss micro-coaxial transmission line is designed to compose the feed network. To improve the bandwidth of the antenna element, a micro-coaxial twin-feed structure with two equal-amplitude and in-phase probes is designed to feed the patch. Artificial neural network (ANN) is applied for antenna element optimization. The 2 × 2 antenna array shows an impedance bandwidth of 6.5 GHz from 57.9 to 64.4 GHz under the condition of voltage standing wave ratio (VSWR) less than 2. The gain of the array is 14.5 dBi at 60 GHz. The total area of the antenna array is 9.58 × 8 mm².

In this paper, cost-effective high-efficiency photovoltaic (PV) power conditioning system (PCS) applicable for small-scale grid tied micro inverters usually under 400 W is proposed. The two-stage PCS consists of a modified H-bridge topology producing 5-level output and a boost converter magnetically-coupled with a secondary charge-pump circuit to provide charge balancing with isolation. Compared to the previous multi-level micro-inverter systems, the inverter circuit has reduced the part count, the DC-DC stage enables Maximum Power Point Tracking (MPPT) without power-conversion efficiency compromise during the voltage balancing operation at the neutral point of the DC-link capacitor for a low-cost 5-level photovoltaic inverter. Also, the voltage ratios are automatically maintained by the coupled-inductor turns ratio, thereby eliminating the additional control circuit for maintaining voltage balancing. Proposed micro-inverter topology is proved by the simulation and hardware prototype experiments.

A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL’s power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

In this study, a microcontroller-based battery test system for power battery is realized. The system is composed by a microcontroller, a sampling circuit, a human interface and a resonant load. The proposed resonant load having wide-range slew-rate and continuous loading features is used to verify the dynamic characteristics of the power battery thus can recycle energy in diagnostic process. Furthermore, the system can provide loading current according to battery specifications. The proposed system has both low cost and portable feature. Finally, this work provides analysis of operation principle, and test results to verify the theoretical feasibility.

The effects of parasitic inductance of transistor on finite dc-feed inductance type class E microwave power amplifier is analyzed in this letter. We find that the frequency bandwidth can be improved by fully consideration of the output parasitic inductance of transistor. To validate the method, a GaN power amplifier by using the proposed topology is designed for demonstration purpose. Experimental results show that the amplifier is realized from 2.5 GHz to 3.5 GHz (33.3%) with measured drain efficiency larger than 60%, which show good agreement with the simulated results.

In this paper, the simple multi-frequency charge pumping (CP) technique in conjunction with the tunneling model of trapped charges shows for profiling of the near-interface oxide traps in gate metal/high-k dielectric/SiO2 interfacial layer stack structure. The methodological basis and the accurate model are introduced for analysis of measured multi-frequency CP data in dual-layer gate oxide. The whole models are derived from the fundamental physics and simplified method is introduced for extraction of the trap profile in the stacked gate dielectric from multi-frequency CP curves.

This paper describes a single-stage AC/DC Power Factor Correction (PFC) converter with galvanic isolation, and an active-clamp circuit is used to achieve zero-voltage-switching (ZVS) for both main and auxiliary switches. The ZVS operation principle of the system is illustrated in detail. Simulation and experimental results based on a 85 kHz, 3000 W prototype circuit show that the proposed converter has low component count, galvanic isolation, simple control, high power factor and high conversion efficiency in a wide load range.

There are various limitations on the supporting tools and design methodologies for the implementation of an asynchronous delay-insensitive model. In this paper, we propose a new design flow by exploiting a mixed model, which combines a bounded delay model and a delay-insensitive model. To develop the design flow, we use an asynchronous finite-state machine for the bounded delay model and the null convention logic for the delay-insensitive model. Further, we designed an MSP430 core to verify the proposed design flow and the results of simulation show that it exhibits a performance improvement of 30.34% over its synchronous counterpart.

This paper proposes a modified Doherty power amplifier (DPA) configuration for bandwidth and efficiency operations. To mitigate the efficiency degradation resulting from the incomplete load modulation network (LMN) and the knee voltage effect, the carrier transistor’s optimum load impedances based on related constant voltage standing wave ratio (VSWR) circle theory are introduced. Meanwhile, a innovative LMN with broadband matching technologies is adopted, which plays a guiding role on the bandwidth expansion from the theoretical point of view. In order to verify the practical feasibility of the design scheme, two 10 W GaN HEMT transistors are used to design a broadband DPA. The measurement results show that the working bandwidth of the power amplifier is from 1.6 GHz to 2.6 GHz. The saturated output power of the whole frequency band is about 41.7–44 dBm and the drain efficiency (DE) is more than 50.8% at the input power of 33 dBm. In addition, the DE is 41.5–45% at 6-dB back-off power. Measurement results verify that the proposed enhancement techniques of bandwidth and efficiency are effective for DPA.

This paper presents a high gain, medium power amplifier for D band application based on 0.5 µm composite collector InP double heterojunction bipolar transistor (DHBT) process. The power amplifier has four ways that combined with a T-junction power combiner. And each way has four stages HBT to provide a high gain performance. The measurement results demonstrate a peak gain of 23.6 dB at 75 GHz and at 140 GHz the gain is 21.89 dB. The saturation output power is 13.7 dBm at 140 GHz with DC power consumption 250 mW.

This paper introduces a novel method of waveguide-mode wireless power transfer (WPT) in a shielded space with an aperture plane. First, it is shown that the simplified model of the engine compartment behaves as a ridge waveguide. Next, the WPT efficiency at the resonant frequency of the dominant mode in the ridge waveguide is discussed using a monopole probe and a helical probe. The results obtained from these simulations and measurements indicate a possibility that WPT efficiency can be improved by our method. Finally, it is experimentally demonstrated that the line-of-sight and non-line-of-sight wireless sensors can operate using our method.

A 1–20 GHz distributed power amplifier (DPA) with a novel compact structure is designed and implemented in a commercial 0.18 µm CMOS technology. The proposed DPA consists of two distributed amplifiers (DAs), which have separate input artificial transmission lines (ATLs) but with their output ATLs shared to achieve high output power and efficiency in the wide frequency band. The gradually changed output ATL is used to further improve the power performance. Measurement results show that the DPA achieves 9.6 dB average associated gain from 1 to 20 GHz. The output power at 1-dB output compression point (OP_1dB) is more than 8.2 dBm, and the peak power-added efficiency (PAE) is 9.6% with the OP_1dB of 12.9 dBm at 4 GHz.

In this letter, a compressive sampling system, which can acquire chirp signal without the prior information of carrier frequency and chirp rate, is proposed. The system first estimates the chirp rate based on windowed modulated wideband converter (MWC). When chirp rate is derived, the system can de-chirp the target signal. Then, the de-chirped signal is acquired by sampling module of the system. Finally, basedon samples, the original signal can be reconstructed by a greedy iteration algorithm which has an adaptive halting condition. Simulation results show the system is capable of estimating chirp rate and reconstructing original signal.

This paper presents a self-gated error resilient cluster of sequential cells (SGERC) to sample the critical data in wide-voltage operation for EDAC system. SGERC introduces latch-based clock gating technique to error resilient circuits and proposes a customized clock gate which has the ability of timing error self-correction with only two additional transistors added for the first time. Further, it totally eliminates the timing error detection circuits required by each critical register before and utilizes the data-driven clock gating circuits to generate timing error information. Simulation results show that SGERC design achieves 58.3% energy efficiency improvement compared with the baseline design and 19.4% over the latest EDAC design.

This paper presents an energy-efficient 500 kS/s 8-bit SAR ADC with a novel dynamic comparator. The proposed dynamic comparator employs a cross-coupling cascode based preamp and an inverter-based pseudo-latch. This approach achieves a 40% higher speed, a 24% lower power consumption, and a similar input-referred noise level, compared with a conventional double-tail dynamic comparator. Moreover, only one single phase clock is required for the proposed comparator. The prototype ADC was fabricated in a 0.5 µm CMOS process with an active area of 0.18 mm². Operating under a 1.8 V supply with Nyquist frequency input signal, the ADC consumes 18.2 µW at 500 kS/s and achieves SNDR and SFDR of 47.5 dB and 63.2 dB, respectively. Walden FoM of 188 fJ/conv.-step is achieved.

Motivated by improvement of convergence characteristics and throughput, this work develops a delay-optimized VLSI realization of the adaptive filter based on the 2-parallel delayed LMS (PDLMS) algorithm. The proposed design uses a novel parallel FIR filter structure based on the fast FIR algorithm. The throughput of the proposed architecture is not only two times that of the traditional structure at the same frequency, but also the convergence characteristic is close to that of the LMS algorithm. The fine-grained dot-product unit, fine-grained fused multiply-add unit and multiple-input-addition unit are adopted to reduce the latency of critical path. From the ASIC synthesis results we find that the proposed architecture of an 8-tap filter has nearly 25% less power and nearly 24% less area-delay-product (ADP) than the best existing structure.

Although the typical sensor-server model has been widely used in intelligent-surveillance applications, the workload increases for the centralized server as the number of sensors increases; therefore, the provision of a scalable performance requires the distribution of the centralized-server workload into the sensors. Due to the limited resources of the sensor side, however, a resource-efficient real-time processing technique is required. In this paper, a real-time sensor-side surveillance technique for which parallel processing is used on CPU-GPU hybrid-computing devices is proposed. The experiment results reveal that the proposed method can provide a real-time execution of the surveillance system.

Taking into account the birefringence effect, the sensing models of phase shifted fiber Bragg grating (PS-FBG) under ultrasonic wave from arbitrary excitation angle were established, and its reflection spectrums were analyzed by simulation based on the transfer matrix principle. Under the excitation of transverse ultrasound, the PS-FBG sharp dip was split into two peaks due to birefringence, the split point spacing increased with the transverse force; under the effect of the ultrasonic wave from random angle, the PS-FBG signal intensity and the ultrasonic excitation angle presented a Cosine curve with two peaks in the middle. Finally, the relevant conclusions were verified by experiments and 12.11 MHz ultrasonic wave was obtained by PS-FBG.