Spectral band replication (SBR) is an effective tool for low bitrate audio codecs such as HE-AAC and enhanced aacPlus. We propose a new algorithm for the bitrate reduction of SBR, which modifies the envelope data coding of SBR considering the threshold in quiet and the masking threshold. Experimental results show that the proposed algorithm significantly reduces the bitrate compared to the conventional SBR with no degradation in perceived sound quality.

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Lifting Scheme based 2-D Inverse Discrete Wavelet Transform 2-D (IDWT) core for JPEG 2000 is implemented into FPGA following a new approach of reusing hardware components. The approach leads towards higher area efficiency and speed optimization. Design realized by Le-Gall 5/3 filter, achieved significant acceleration that executes at over 300MHz with 7.13Msamples throughput whereas using less than 1% of logic elements in Altera Stratix II FPGA. High quality reconstructed image are extracted from Matlab and VHDL simulations. Implementation details of the individual hardware blocks, synthesis result, and performance analysis are presented.

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This paper presents an optimized mapping of pixels into the external SDRAM for H.264/AVC video decoding. The modern SDRAM system usually employs the burst-access mode as well as the multi-bank architecture to improve the utility efficiency. If the accessed video pixels can be placed uniformly and successively across different memory banks, both of them will be used with high efficiency. Based on a statistic method, this paper traces and analyzes the actual memory accesses of H.264/AVC decoding and gives an optimized placement of pixels in the SDRAM—the optimized data unit is 8x8. Moreover, the efficiencies of the optimized cache and pre-fetch technologies are also evaluated, which show that this optimization can improve both the cache hit ratio and the pre-fetch effect apparently.

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In this paper, a flexible, high computation speed and cost effective field programmable gate array (FPGA)-based speed controller for an induction motor with field-oriented control, (FOC) is presented. All the control functions including the space vector modulation based PWM waveform generation, field-oriented control algorithm and rotor flux position estimation have been realized using FPGA to reduce the total part count of the hardware prototype and hence provide a low cost solution. The constructed FOC IC consists of 6844 logic elements and is realized using Cyclone, EPIC12q240C8 from Altera Inc. The sampling rate can be programmed up to 100MHz. Experimental result is included in this paper to illustrate the performance of the designed IC, FOCIC and the feasibility of integrating of SVM and FOC on single chip.

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In this paper we describe a new superblock management scheme to overcome the problem of increased erase operations, that results from increasing the degree of interleaving of memory banks in flash memory based storage devices. To improve performance, superblock management is used to increase the degree of linear interleaving of flash memory banks. However, increased interleaving may significantly increase the number of erase operations, thus decreasing device lifetime. The proposed management scheme efficiently separates hot and cold data into two different sub-groups, dramatically increasing the efficiency of superblock merging. According to our simulation results, the number of erase operations decreases by around 27.3 percent, which is enough to significantly lengthen overall device lifetime. Read performance is only slightly degraded by our approach.

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In this paper, we propose a new negative charge pump circuit which is based on the Dickson circuit. This circuit overcomes the limitation of the conventional Dickson pump circuit and doubler-based one such as large loss in output voltage, low power efficiency, and small output current. Comparing the new one with the conventional doubler-based circuit at the V_DD=8V indicates the pumping time faster by 83.8%, 7 times larger output current, power efficiency better by 23.1%, and the layout area smaller by 15%. We have verified the new pump circuit using the commercial CMOS process with high-voltage devices.

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This paper presents a new derivative superposition scheme for simultaneous cancellation of second and third-order distortions in common-gate transconductance stage of mixer, addressing the challenging dynamic range required in multi-mode front-end CMOS circuits. Using Volterra series analysis, the unsatisfactory results of conventional derivative superposition in common-gate structures, and thus the need for simultaneous cancellation is investigated. An inductor interposed between two transconductances tunes out the parasitic capacitors and improves conversion gain. Simulation results of proposed mixer in a 0.13µm-CMOS technology with 1.2V supply illustrate 16-dB improvement in IIP3 and 30-dB increase in IIP2 compared to conventional Gilbert mixer.

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In this paper, we propose a configuration for the two dimensional array of multi-degree-of-freedom (MDOF) ultrasonic actuators suitable for two-dimensionally moving table. The MDOF motions of a ball rotor are achieved by the combination of two bending and one longitudinal vibrations excited on columns fixed on a substrate. A 2 x 2 array of MDOF column actuator is fabricated for two-dimensional movement of a plate placed on the array. Only one piezoelectric element is used for one column instead of a stack of different types of PZT elements to drive the vibrations. First, we describe the configuration of the actuator, an excitation method of each vibration, and the operating principle of the stage motion. Then, moving table operation was demonstrated and evaluated.

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In this paper, a new technique is proposed for multiplication of two sampled low frequency analog signals and the result is in digital form. Out of the two signals, one signal is fed to the input of typical second order, ΔΣ Modulator (DSM). The operating period of the DSM circuit is varied directly in proportion to the absolute amplitude of the second analog signal. In this case, the average value of the digital output of quantizer is equal to the product of the analog signals in each sampling period. The dynamic range of input signals and the accuracy of proposed multiplier are better than the conventional CMOS multipliers.

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In this paper, a novel versatile active building block the differential-input buffered and transconductance amplifier (DBTA) is proposed. The application of the newly defined active function block is shown on the design of voltage-mode (VM), multi-input and single-output (MISO)-type multifunction biquad, employing single DBTA and five passive elements. Proposed VM filter structure can realize four filter functions i.e., low- (LP), band- (BP), high-pass (HP) and band-stop (BS) without changing the circuit topology and enables independent control of the quality factor Q using single passive element. Theoretical results are verified by PSPICE simulations using a BJT realization of DBTA.

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This paper presents a new technique for improving the quality factor of conventional active inductors by using the drain-source capacitance of a MOSFET in the cut-off region. This inductor is utilized to design a tunable notch filter for interference rejection in UWB LNA. Using a 0.13µm CMOS technology, simulation shows that the notch frequency can be tuned for about 1GHz frequency range, and the quality factor is improved more than one order of magnitude compared to conventional active inductor. The power dissipation of the new active inductor is 2.4mW from 1.2V supply.

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To improve the near-infrared sensitivity of an image sensor that has a conventional pixel structure, we made use of the metal wiring layer as a reflector in addition to the method of back-side illumination from the etched back surface of the sensor. We fabricated an image sensor that has a remaining silicon substrate thickness of 32 ± 4µm and evaluated the spectral sensitivity. For 830nm light, the sensitivity is about the same as for front-side illumination. For a wavelength of 970nm, the sensitivity was 2.2 times as high as for front-side illumination. The image sensor with reflector has about 30% higher sensitivity than without the reflector.

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Existing indoor power-line grids are a potential solution to the last mile problem for broadband communication providers. However, power-line communication (PLC) channels suffer from deep frequency notches and severe impulsive noise making powerful signal processing essential if these channels are to be utilized. Broadband communications using Multicarrier Code Division Multiple Access(MC-CDMA) with channel coding is considered. Although resilient to frequency-selective fading, the coding gain from turbo signal processing is substantially compromised in the presence of impulsive noise. To overcome this, we propose a low complexity non-linear matched filter utilizing M-estimation technique. We will show that this matched M-estimate filter is indispensable in providing efficient baseband filtering in impulsive channels.

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We derive a novel time-domain asymptotic solution for a transient scattered field by a cylindrically curved conducting surface by extending the corresponding frequency-domain asymptotic solution. The transient scattered field is excited by the high-frequency modulated pulse source. By comparing the asymptotic solution with the reference solution calculated numerically, we show that the novel time-domain asymptotic solution is highly accurate and very efficient in terms of the computation time. We also show that the time-domain asymptotic solution is easy to understand the physical insight of the scattering by the cylindrically curved surface.

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