To validate the performance of the optical system of the tested equipment, the airborne multi-light source steering device needs to track the mounted equipment on other aircraft during flight tests and provide it with five beacon lights with a maximum span of more than 2 meters and parallelism less than 0.3°. The design, calibration, and flight environment of the airborne multi-light source steering device can affect its pointing accuracy. To address this issue, this paper studies the pointing accuracy of the device, separates its errors, and proposes a method based on the combination of multi-body system theory and finite element simulation. By establishing a mathematical model of pointing errors and relying on finite element simulation to simulate real-world working conditions, the dynamic pointing error patterns are analyzed. Finally, the method is validated through experiments. In the ground dynamic tests, the device’s pointing accuracy is 0.2099°, and during the flight tests, the pointing accuracy is 0.231° with an accuracy rate of 90.86%. This proves that the proposed method is highly reliable and accurate.

We have introduced a sub-nanometer non-contact displacement sensing method using phase-diversity optical digital coherent detection. The initial work achieved 0.62nm displacement sensing with a 0.21nm resolution using a temporal domain filter. However, optimizing the filter for a sharp transition band and low order posed challenges, limiting noise filtering. To overcome this, frequency-domain filter is proposed and investigated in this work. Employing a frequency-domain bandpass filter improved resolution to 0.07nm at 0.62nm displacement, resulting in an 18.5dB signal-to-noise ratio--8dB higher than temporal domain filtering. This advancement enhances precision for applications in precision instruments without any additional cost.

This work presents a novel digital intermediate frequency (IF) module designed for hyperspectral microwave radiometers, enabling the detection of non-uniform channels. The IF module is based on polyphase filter bank and fast Fourier transform techniques, capable of processing sampling data from high-speed analog-to-digital converters (ADC) in real time. The module is implemented on a circuit board featuring a 6.4 gigabit samples per second sampling-rate ADC and Xilinx Vertex-7 field programmable gate array, followed by performance testing and analysis. When combined with an appropriate radio frequency front-end, this IF module can form a hyperspectral microwave radiometer with non-uniform channel detection capability, finding applications in various microwave remote sensing fields.

Nanopore-based DNA sequencing technology features the advantages of label-free, low-cost, and rapid detection. However, the existing nanopore sequencing readout cell or array for the lower area and power consumption become prohibitive. This brief presents a low noise potentiostat readout array. Based on the five-transistor OPA, the half-shared amplifier reduces the area and power consumption of the cell by about 50%, and shows a good suppression effect on mid-to-high frequency noise in the output channel. As a result, high-throughput is achieved with low noise. The performance of the proposed array channel has been evaluated in 180-nm CMOS process, the input-referred current transient noise was 2.28pARMS, the power consumption was 2.2µW and the unit area was 10×12µm².

This paper presents a new method to overcome the degraded control performance of linear induction motors (LIM) due to end effects. The method employs a parameter-self-tuning adaptive sliding mode observer (ASMO) and model predictive current control (MPCC), which first develops a LIM mathematical model considering end effects and then designs the MPCC to strengthen the control. To improve the accuracy of the flux observation, the method develops the ASMO and analyzes the stability of the observer. For parameter tuning, the method utilizes an improved particle swarm optimization algorithm (IPSO). Overall, the experimental findings validate the effectiveness of the proposed algorithm.

A cascaded linear active disturbance rejection control multi-stage model predictive control (CasLADRC-MSMPC) method is proposed to provide faster speed and current response, as well as stronger disturbance suppression ability for permanent magnet synchronous motor (PMSM) systems. Firstly, based on the analysis of the discrete mathematical model of PMSM, a multi-stage finite set MPC algorithm is proposed. Secondly, the control performance of the traditional LADRC (TLADRC) algorithm and cascaded LADRC algorithm is analyzed, which provides an excellent controller for the MSMPC algorithm. The MSMPC algorithm is then subjected to the cascaded LADRC algorithm in order to enhance the overall control system’s performance and anti-interference capability. Finally, experimental analysis is conducted on the TLADRC-MPC strategy, CasLADRC-MPC strategy, and CasLADRC-MSMPC strategy. The experimental results show that the proposed algorithm has better current tracking ability and stronger anti-interference ability.

This letter presents a broadband, high-precision bidirectional passive 6-bit digital phase shifter (DPS) designed for phased array systems. We propose three novel structures: the dual modified magnetically coupled all pass network (DMMCAPN) for small phase shifts, the modified high pass network/modified magnetically coupled all pass network (MHPN/MMCAPN) for medium phase shifts, and the Lange/modified transmission line network (L/MTLN) for large phase shifts. It shows a phase shift range of 360° with a step of 5.625°. Measurements in the 6.5-13.5GHz range indicate that the root-mean-square (RMS) phase and amplitude errors for the 64 states are within 1.8° and 0.75dB, respectively. Additionally, the average insertion loss is (-12.2±0.5)dB and the input 1dB compression point (IP1dB) is 29dBm at IF 10GHz. To the best of our knowledge, this letter presents an exceptionally high degree of phase shift accuracy across the broad bandwidth, outperforming other GaAs passive digital phase shifters. Furthermore, it showcases superior linearity when compared to silicon-based passive digital phase shifters.

Thinning of phased only rectangular planar array can reduce the cost and simplify the radio front end of the array. Therefore, it is reasonable to develop the thinning pattern synthesis approach for phased only rectangular planar array. In this letter, a novel computational approach is presented to form the beam pattern and thin the phased only rectangular planar array. First, a new simple matrix equation based on two-dimensional Fourier transform (FT) is derived to calculate the antenna element excitations and the beam pattern. Then, the computational steps to obtain the antenna element excitations with uniform amplitudes are presented. In order to increase the attenuation of the side lobes, the target beam pattern with varied phases determined by a novel analytical formula is proposed. Two examples are used to demonstrate the advantages of the new method. The simulation results show that the new approach can synthesize the beam pattern well, and the new pattern synthesis method has good performance in thinning the phased only rectangular array.

This paper proposes a wide-band and wide-angle scanning Ku/Ka dual-band phased-array antenna. The dual-band antenna array consists of Ka-band PCB-based slot antenna elements and Ku-band metallic banyan tree antenna elements. The operating bandwidth of both bands is extended to 4GHz, and the beam scanning coverage achieves ±60° and ±30° for Ku and Ka bands, respectively. By special treatment of the PCB, the channel isolation between Ku and Ka elements is better than -30dB and -18dB in two bands, which can support the simultaneous working situation of both antennas. Besides, the feeding structures of both antennas are flexible to be utilized in a phased-array system. A prototype of Ku/Ka antenna array is also fabricated. The measured active VSWR, channel isolation and scanning patterns are in good agreement with the simulated results, which demonstrates its good radiating performance and indicates the promising application in advanced phased array systems.

In this work, the design of a 0.18µm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100µA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500µA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.

In this study, we proposed a method that could efficiently and comprehensively evaluate power-performance-area (PPA) characteristics of CMOS processes across multiple technology nodes. According to the International Semiconductors Technology Roadmaps (ITRS), we have designed and implemented a series of benchmark Ring Oscillator (RO) circuits using a full-scale downsizing approach from 180nm half-pitch node to 28nm node. Simultaneously, we conducted simulations, analysis, and layout design for RO circuits based on six low-leakage (LL) processes: 180nm, 130nm, 90nm, 65nm, 40nm, and 28nm processes. Through longitudinal analysis and comparison of the PPA characteristics across these six processes, the process quality can be better understood, and some reliable conclusions can be drawn to guide design metrics. The proposed method and benchmark circuits can be well extended to future advanced technology nodes.

A novel capacitor-less low-dropout regulator (CL-LDO) is presented that achieves transient and stability enhancements through the addition of an active capacitor and a dynamically biased buffer. To enhance the transient response, an active capacitor is proposed, resulting in a significant reduction in overshoot, undershoot, and settling time. Furthermore, the dynamically-biased buffer, comprised of a super-gm source follower, effectively enhances the loop stability. Implemented and fabricated in 0.18µm SOI BCD technology, the CL-LDO generates a stable output voltage of 1.8V in the input voltage range from 2.8V to 3.8V, with a maximum load current of 100mA and a quiescent current of 94µA. When the load current steps from 0mA to 100mA, the measured results of overshoot and undershoot are 240mV and 110mV, respectively. The proposed CL-LDO has superior line regulation of 0.94mV/V and load regulation of 12.66mV/A.