This paper presents a low dropout regulator (LDO) with a low quiescent current which helps to extend the standby time of battery-powered electronic devices. By utilizing the switchable bias technique in the error amplifier (EA), the bias current is switched to a higher level to accelerate the transient response under heavy load, while a low bias current is applied to EA to maintain a low quiescent current under light load. High speed current comparators and hysteresis control are combined to ensure fast and stable switching operation of the bias current. Moreover, an inrush current suppression circuit is proposed by recycling the switchable bias in EA. During startup, the bias current of EA can be kept low, and a reduced slew rate can be obtained at the pass gate voltage. The proposed LDO has been fabricated in 0.18-µm CMOS process, The experimental total quiescent current is 300nA under no-load condition. The maximum load current is 300mA. Measurement results show that the LDO can be settled within 8µs for a load current step of 0-50mA. In the startup process, the measured inrush current can be effectively limited.

This letter reports on experimental results of high data rate transmissions using a sub-terahertz single-carrier (SC) transmission scheme. One requirement for 6G is achieving a data rate exceeding 100Gbps. According to Shannon’s channel capacity, the data rate is proportional to the transmission-signal bandwidth. Therefore, one approach for achieving the target data rate is to employ a sub-terahertz transmission with an ultra-wide bandwidth of over several gigahertz. To verify the feasibility of high data-rate transmission using an ultra-wide bandwidth, a SC transmission system with a carrier frequency of 141.5GHz is configured and tested in an outdoor line-of-sight environment. The configured system transmits two different wideband signals using orthogonal polarization-division multiplexing. Experimental results show that a single vertical or horizontal polarized transmission with a baud rate of 10GHz is available for the data rate of 60Gbps at the long transmission distance of 100m. Furthermore, the total data rate of 117Gbps is achieved by multiplexing two orthogonally polarized transmissions.

This paper presents a 10-bit 40MS/s successive-approximation-register analog-to-digital converter (SAR ADC). To enhance the performance of the ADC, a high-linearity CMOS complementary bootstrap sampling switch (B-CMOS-SW) and a low-offset, low-noise double-tail dynamic comparator (LOLN-DT) are proposed. The ADC with the proposed comparator and the bootstrap switch is fabricated in a 40-nm 1P6M CMOS technology. Simulation results show that the proposed comparator achieves a low offset voltage of 3.4mV at 1σ, which reduces half compared with conventional Double tail (DT) dynamic comparator, and the input reference noise is 0.3mV at 1σ. Also, the proposed bootstrap switch improves the sampling nonlinearity above 6dB. At 1.2V supply and 40MS/s, the ADC reaches a SINAD of 57dB, the SFDR reaches more than 70dB, and the power consumption is 0.2mW, leading to a figure-of-merit (FOM) of 9.76fJ/conversion-step.

A dual-mode buck converter with dynamic sawtooth voltage is presented in this paper. The proposed design can handle loads from 10mA to 1000mA by utilizing PSM and PWM modes. Moreover, there is hysteresis during mode switching from PWM to PSM to avoid the control mode fluctuating. Dynamic sawtooth voltage is used to address the line transition issue over a wide input voltage range. Implemented in 0.25µm BCD technology, this converter can generate an output voltage of 5V with an input voltage range of 10-55V. The simulated results demonstrate the proper mode transition under step-up/down load current transient. The peak efficiency is 92.57% at 90mA. The load regulation and line regulation are 1.07µV/mA and 15.2µV/V, respectively.

The P-mode is the bottleneck restricting the DSC encoder’s encoding rate to 1pixel/clock. To enhance encoding efficiency, we improve the MMAP algorithm of DSC, then present a parallel P-mode circuit design based on the algorithm that enables processing 3 pixels in parallel. The algorithm test result indicates a marginal decline in PSNR by 1.15%. The synthesis result reveals that the circuit achieves 2.92 times the efficiency of the serial P-mode circuit we designed, with a 32.29% increase in area and 41.80% in power consumption, or about 1.14 times the efficiency of the DSC encoder chip at 0.38 times frequency.

This paper presents a VCO-based second-order feedforward CT-ADC architecture designed for EEG recording front-ends. This structure permits the first-stage integrator to process only the quantization noise, thereby enhancing its linearity. A dead-band switch and gain stage are added between the input and DAC feedback ends, effectively reducing the ripple effects caused by chopping and the noise introduced by feedforward. To validate the proposed architecture, an ADC was fabricated using a 65nm CMOS process, achieving an SNDR of 84.5dB, a DR of 94.6dB within a 10kHz bandwidth, and the smallest chip area of 0.026mm². The ADC consumes 7.22µW of power from a 1V supply, achieving an SNDR performance value (FoM) of 175.9dB for the VCO-based ADC.

An electron injection enhanced bi-mode MOS controlled thyristor (IE-Bi-MCT) structure is proposed by introducing a n-type carrier storage (CS) layer under the p⁺⁺ diverter region of BRT to prevent the extraction of holes during conduction, which leads to the electron injection enhancement (IE) effect similar to IGBT. This is beneficial to the holes accumulated at n CS layer being swept into the p-base region, and the voltage drop across the lateral resistance of the p-base region is increased, which causes the thyristor to be quickly latched up, thus IE-Bi-MCT is converted from IGBT mode to thyristor mode. As a results, the snapback phenomenon is suppressed during forward conduction and conduction loss is significantly reduced. The simulation results show that the snapback phenomenon can be eliminated under the proper parameters of n CS layer, and the on-state voltage drop decreased by about 38% compared with the conventional BRT under 30A/cm² current density.

Spiking Neural Network (SNN) accelerators, recognized for their potential in neuromorphic processing, have yet to fully realize high energy efficiency, especially in widespread conventional non-event-based tasks, thus limiting their broader applicability. In response, we introduce an effective, cost-efficient method named dynamic predictive early stopping. This method enhances energy efficiency by predicting and stopping nearly 70% of non-essential computations during inference while ensuring near-lossless performance. The FPGA-based accelerator prototype demonstrated a 35% energy efficiency net improvement (to 208.74GOPS/W, leading for its class). Simultaneously, the proposed method incorporates only minimal (<0.41%) extensions to hardware. With potential for further improvements and explorations, this method could bring substantial impact by being widely adopted by SNN accelerators.

In this letter, a compact 2-18GHz ultra-wideband frequency-conversion transmit/receive (T/R) module based on a three-dimensional heterogeneous integration (3DHI) process is designed and fabricated. An ultra-wideband impedance matching method is introduced to address the structural discontinuities within the 3D interconnections. Through silicon via (TSV) shielding and cavity designs are leveraged to reduce the impact of local oscillator (LO) leakage. The compact module consists of stacked four-layer silicon interposers and two-layer embedded chips is employed by a 3DHI process with wafer-to-wafer (W2W) bonding, the dimensions of which is only 10.1mm × 10.1mm × 1.0mm. The measured results show that the saturated output power reaches 19dBm at 2GHz and 16.9dBm at 18GHz, and the rejection of image frequencies exceeds 70dBc.

Logic locking is an integrated circuit hardware protection technique aimed at combating reverse engineering, IP piracy, and hardware Trojans. Cyclic encryption, one of these techniques, is designed to create feedback loops in circuits to resist SAT attacks, but it was quickly compromised. In this paper, we introduce a new cyclic logic locking method, FCLock, which effectively renders SAT/CycSAT/BeSAT decryption techniques obsolete. By altering the encoding of the state machine that drives the combinational logic circuits, we functionally preserve the non-combinational logic loops. This preservation makes it impossible for attackers to decrypt the circuit by removing cycles. Experimental results demonstrate the effectiveness and security of the proposed method, as well as its low overhead.

This paper presents a novel hardware-efficient cochlea model designed as a multi-compartment basilar membrane (BM) whose dynamics is described by coupled ergodic sequential logics (SLs). The following comparisons of the presented model yielded useful results in developing a small and low-power cochlear implant that reproduces nonlinear hearing characteristics of the human cochlea: 1) a comparison with a conventional one designed as a single-compartment BM whose dynamics is described by coupled ergodic SLs revealed that the nonlinear hearing characteristics of two-tone responses in the presented model are closer to those of a biological example; 2) a comparison with a conventional one designed as a multi-compartment BM whose dynamics is described by an ordinary differential equation revealed that fewer circuit elements and less power in the presented model are required for implementation on a field-programmable gate array and its operation, respectively.

This paper proposes a method based on transfer function to monitor the solder layer void damage in IGBT modules. Firstly, the thermal resistance of each layer structure of IGBT module and the Cauer model is analyzed. Secondly, the process of obtaining the parameters of Cauer model by transfer function is analyzed. Finally, the thermal resistance of the IGBT module under different void fractions of the solder layer is measured by experiments, which obtains the relationship between the thermal resistance difference and the void fractions. In addition, this method is compared with the monitoring method by IEC standard, which verifies the accuracy and feasibility of this method.

In this paper, a novel dual-loop control scheme is proposed to improve the voltage tracking performance of DC-DC boost converters. According to the conventional super-twisting algorithm, a new modified fast super-twisting algorithm (FSTA) is developed which is introduced in the strategy to enhance the convergence performance. On the basis of FSTA, a second-order sliding mode controller is designed in the inner current loop. The outer voltage loop controller consists of a nonlinear PI controller and a fast super-twisting sliding mode observer, which generates the reference current value. The uncertain terms are estimated by the fast super-twisting sliding mode observer and compensated to the outer voltage loop. Simulation results are carried out to confirm the effectiveness and superiority of the proposed control strategy.