We report CW single-wavelength emission at RT from non-grating active multi-mode interferometer laser diodes (MMI LDs) by using an asymmetric configuration. Fabricated devices showed side-mode suppression ratio (SMSR) of 31dB (λ=1.56µm). We also present the modulation characteristics of this novel device at 1.25Gbps for a 2⁷-1 pseudorandom binary sequence.

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Digital predistortion is an efficient and robust technique for improving the linearity of power amplifiers. In this paper, we propose a digital predistorter based on frequency domain for OFDM signals, which exhibits superior accuracy against the predistortion in time domain. Simulation results show that, the desired MER can be achieved with fractional delay error as large as 6% of sampling time. It is also shown that since in frequency domain a fractional delay translates to phase rotation, phase rotation estimation and compensation can be performed by a low complexity scheme. Comparison of implementation complexity in frequency domain against time domain illustrates an improvement of approximately 60%.

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Many-core processor based systems gain popularity in high-performance parallel embedded applications. Estimating memory bandwidth requirement, i.e. external memory bandwidth, given various cache size for target parallel applications requires a prohibitively large simulation time. In this work, we propose an analytical model to quickly estimate the memory bandwidth for a given cache size and help exploring trade-offs between cache sizes and memory bandwidth requirement. We model the stochastic behavior of cache misses for a single cache as a random process. Using central limit theorems for identically or non-identically distributed random processes, we accurately estimate the collective cache misses from hundreds of processor cores and thus the total memory bandwidth requirement for the whole system. The results show that our model improves a speed of simulation time up to 200.4 times for 200 cores whereas its estimated results achieve less than 0.01% difference from the simulated ones for 200 cores in terms of accuracy.

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This paper proposes a high-throughput intrusion detection system (IDS) with a bloom filter-based header comparison and parallel pattern matching for the packet content. The parallel pattern matching is a two parallel sequence comparison architecture that compares the packet content with the Snort rules. The proposed hardware IDS not only performs high throughput, but also reduces the rules memory size. As shown in post-layout simulation of the implemented application-specific integrated circuit (ASIC), the speed reaches 453MHz that performs 7.2Gbps system throughput to deal with the traffic requirement of edge speed in end user network. With 8MB off-chip SRAM, the system supports 4,020 Snort rules that the pattern number is enough for intruder signature.

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Coherent optical two-tone generation using an optical frequency comb generator based on an amplified optical fiber loop is successfully demonstrated. The observed phase noises in the 100-GHz band are less than -80dBc/Hz at 1MHz. This method is suitable for high-speed radio communication based on advanced modulation techniques.

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In this paper, we proposed a new structural protective device based on a silicon controlled rectifier (SCR) to protect ESD (Electrostatic Discharge) of an integrated circuit. The proposed device features latch-up immunity in a normal operation state by the low holding voltage of the existing SCR - based PSD protective device. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in terms of individual design variables (D1, D2, D3). As a result of the measurement, we were able to increase the holding voltage from 15.75V to 19.35V to the maximum depending on the length adjustment of design variables and checked the high robustness of the secondary breakdown current more than 4.6A with tolerance robustness. The proposed ESD protective device was made using 0.18µm Bipolar-CMOS-DMOS processing.

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An accurate and cost-effective method for ADC jitter estimation is proposed. The new method only requires a single high-frequency test. Eliminating the need for a 2nd low-frequency test in the conventional dual-frequency tests can significantly save both hardware and data acquisition time. Furthermore, the proposed method does not require the condition of coherent sampling and expensive instruments. Theoretical analysis, simulation and experimental results show that the proposed method is cost-effective and can achieve the test accuracy comparable to conventional dual-frequency tests.

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This article deals with investigating research errors and inaccurate results which appear in the article “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it” [1] H. Moradzadeh and S. J. Azhari, IEICE Electron. Express, vol. 5, no. 23, pp. 1017-1023, 2008.

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This article tries to answer to comments delivered by Fabian Khateb et. al. about the article “High performance low-voltage QFG-based DVCC and a novel fully differential SC integrator based on it” [1] H. Moradzadeh and S. J. Azhari, IEICE Electron. Express, vol. 5, no. 23, pp. 1017-1023, 2008.

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We describe the greatly improved performance of a 1.5µm optical frequency stabilized Cs atomic clock composed of a mode-hop-free mode-locked fiber laser and an acetylene optical frequency standard. The output pulse width was shortened from 7.1 to 3.4ps by employing a phase modulator instead of an intensity modulator as a mode-locker. The optical frequency stability for an averaging time of 100s was also improved from 1.8×10^-11 to 6.3×10^-12 by precisely controlling the laser cavity temperature.

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