This paper proposes a directly coupled instrumentation amplifier (IA) for EEG signal acquisition. By integrating both chopping and auto-zeroing (AZ) techniques, an offset and 1/f noise control loop (OFC) structure is proposed. Furthermore, a Capacitive Impedance Boost Loop (CIBL) configuration is presented to augment the input impedance within the EEG frequency band. Using the Common-Mode Biasing Circuit, the common mode rejection ratio (CMRR) of the circuit is improved. Fabricated in a 180-nm CMOS process, the prototype IA has the input-referred noise of 0.12µV_rms from 0.01Hz to 100Hz. The proposed IA achieves high-input impedances of 4.14GΩ at 20Hz, and CMRR of 133.1dB at 70Hz.

This paper proposes a new α algorithm based on Lagrange linear interpolating power prediction. This algorithm ameliorates the conventional power prediction perturbation and observation method, thus enhances system accuracy and reduces errors. Meanwhile, it also has relatively faster transient tracking speed and smaller oscillation than the traditional method. By iteratively tracking the intermediate variable α, the algorithm operating point is close to the factual maximum power point, which can shorten the tracking time. Furthermore, when the external environment changes, Lagrange linear interpolating power prediction method can avoid misjudgments effectively. The algorithm has been verified using Matlab/Simulink software and through experimentation.

A 12-bit successive approximation register-based analog-to-digital converter (SAR ADC) with non-binary search technology is introduced. By embedding redundant weights in the branch capacitors of traditional binary DAC arrays, non-binary search can be achieved without adding additional control logic. Enables fast conversion with low overhead and tolerates the problem of incomplete stability of the reference voltage. Divide the MSB capacitor equivalently and use a hybrid capacitor switch to reduce the power consumption of the comparator and the changes in input common mode voltage (VCM). The total capacitance is reduced through the use of dual reference, avoiding the mismatch caused by the use of small unit capacitance. The ADC achieves an SFDR of 75.61dB and 10.22-bit ENOB with Nyquist input consuming 1.83mW at 1.1V supply, resulting in a figure of merit of 30.69fJ/conversion step.

This paper presents a low-dropout linear regulator (LDO) with ultra-low quiescent current in high-voltage environments. A high-voltage pre-regulation module is employed to provide stable low-voltage output, reducing the use of high-voltage transistors. The integration of error amplifiers and reference circuits effectively reduces quiescent current while reducing chip area. Load detection function is used to reduce the quiescent current of the over temperature protection circuit under no-load conditions. Stability within the full load range is achieved through zero-pole tracking compensation and pseudo-ESR compensation techniques. LDO is fabricated using 0.35µm BCD high-voltage technology and can stably output 5V when the input voltage is in the range of 5.5-24V. The quiescent current at 24V input is 960nA, and it can drive a maximum load of 150mA. The overshoot voltage is less than 61mV during load variations within 100mA.

A laboratory test platform was established to explore the impact of humidity on potential-induced degradation (PID) under ash-covered photovoltaic modules. The mechanism behind changes in leakage current and output power was thoroughly investigated. The results indicate that the combination of dust accumulation on the module surface and humidity significantly elevates the leakage current. Specifically, the leakage current experiences an exponential increase when humidity exceeds 45% (CRH). By utilizing Peck’s equation, the correlation coefficient λ between the power degradation of dust-covered and clean modules was derived. This coefficient can accurately forecast the power loss of dust-covered modules, offering valuable insights for the maintenance of PV power stations.

This paper proposes a high step-up DC-DC converter with a quadratic cascaded coupled inductor. The primary and secondary sides of the coupled inductor are connected in series, and the secondary side of the coupled inductor is combined with the voltage multiplier cell. The main advantages of the converter include high voltage gain, low voltage stress on power switches, continuity of input current, and the common ground between the source and load. The performance of the proposed converter is experimented with using a 220W prototype that converts 25V from the input side to 426V on the output side. The peak efficiency is up to 94.77%.

This letter introduces a fully integrated broadband dual-mode reconfigurable driver amplifier (DA). DA can operate in analog DA mode (ADA-mode) and digital DA mode (DDA-mode) to meet different requirements for linearity and efficiency in various scenarios. A broadband reconfigurable output network enables the DA to operate from 2-4.5GHz providing impedance matching, power combining and harmonic rejection. The DA offers a maximum gain of 12dB with a 5-bit digital-control gain step in 1.6V supply. Measurement results demonstrate that the DA achieves an OP1dB of 8.5dBm with a drain efficiency of 13.1% in ADA-mode. In DDA-mode, the DA achieves a maximum output power of 10dBm with a drain efficiency of 30.8%. The gain error of proposed DA is less than 0.3dB. The DA is fabricated in 40nm CMOS process, and the active area is 0.16mm².