This paper presents a pipelined analog-to-digital converters (ADCs) calibration method that integrates ant colony optimization (ACO) algorithm with time-delay neural network (TDNN). The proposed method uses TDNNs to calibrate the integral nonlinearity error of the ADC, and leverages the global search capability of ACO to optimize the time-delay feature dimensions and the initial parameter configuration of the neural network. This approach improves the calibration performance, reduces the model size, and avoids converging to local optima. The calibration method was evaluated using a commercial 14-bit, 1 Gsps pipelined ADC chip. The results show that this method improves the SNDR from 63.80 dB to 79.31 dB, SFDR from 82.50 dB to 95.65 dB, and ENOB from 10.31 bits to 12.88 bits. Additionally, this method identifies the optimal time-delay feature combination with a 100% probability of global optimal calibration performance.

In this letter, a low-profile substrate-integrated magnetoelectric dipole antenna was designed. Three layers of Rogers 5880 substrates stacked in the longitudinal direction. Electric dipole and magnetic dipole were realized by top rectangular patches and middle meandering structure, respectively. Through a surface current plot, it was found that the electric dipole worked by the electromagnetic coupling from the magnetic dipole, and hence the working mechanism was figured out and a low profile was achieved. By fabrication and measurement, the proposed antenna has a bandwidth from 3.08 GHz to 4.07 GHz (27.7%) for |S₁₁| < -10 dB. Boresight gain is 9.045±0.905 dBi. The profile is only 0.06 λ₀ (λ₀ is the center wavelength). Measurement and simulation agree well with each other. Therefore, the proposed design can be used on the planar communication equipment with low-profile demands.

This paper presents design considerations for electrostatic discharge (ESD) protection diodes in 5 nm bulk FinFET technology. Performance metrics of various diode structures, including gated diodes, STI diodes, and square diodes, are evaluated using 3D TCAD device simulations, focusing on thermal breakdown current, on-resistance, and parasitic capacitance. The simulation results are further analyzed to understand the physical mechanisms influencing these performance metrics. In terms of thermal breakdown current, simulation results indicate that the square diode exhibits the best performance, followed by the STI diode, and then the gated diode. Regarding parasitic capacitance, the STI diode demonstrates superior performance, followed by the square diode, and finally the gated diode.

Theswitching characteristics of four 650 V power devices were compared: (1) Cascode GaN-FET, (2) SiC-MOSFET, (3) Si-SJ-MOSFET, and (4) Si-RC-IGBT. Using double pulse tests, the characteristics of two configurations ((a) Schottky Barrier Diode/Transistor (Tr), (b) Tr/Tr) were evaluated. In both configurations, the Cascode GaN-FET had the smallest switching loss, less than half that of the other devices. The SiC-MOSFET had a smaller transconductance than the other devices, and the turn-on loss in configuration (a) was slightly larger than those of the Si devices. In configuration (b), the turn-on losses of the two Si devices were significantly larger than those in (a) due to the recovery current of the internal diodes of the transistors.

The vibration energy harvesting properties of Fe-based nanocrystalline soft magnetostrictive material (Fe-Si-B-P-Cu-C) thin films were systematically investigated. Thin films were deposited using rotational sputtering and subsequently annealed. Nanocrystallization occurred in the samples annealed at 100-110% of the crystallization temperature. This nanocrystallization process enhanced soft magnetic properties, however, decrease saturation magnetostriction reflecting the influence of the negative magnetostrictive α-Fe phase. The film annealed at 105% of the crystallization temperature exhibited the highest vibration power generation performance. This superior performance was attributed to the combination of enhanced soft magnetic properties, high saturation magnetic flux density, and a relatively large saturation magnetostriction.

A 28 GHz noise-cancelling low noise amplifier (LNA) in standard 65 nm CMOS technology is introduced for millimeter-wave application in this letter. The proposed LNA implements transformer-based noise-cancelling technique to cancel the in-phase noise from main and auxiliary amplifier while strengthening the combined signal. A gain-boosting transformer is employed to improve gain with minimized power consumption. Current-reuse technique is further introduced to reduce power consumption overhead. This work achieves a gain of 27 dB and a minimum noise figure (NF) of 2.5 dB with only 4.4-mW LNA stage power consumption.