Based on scattering cancellation cloaking technology, we developed an illusion cloaking design mechanism for complex-shaped targets of electrically moderate or large sizes, which was achieved by combining transformation optics with the characteristic mode method. Using the transformation optics theory, the electrical size of an object can be reduced under the premise of an identical electromagnetic scattering pattern. Subsequently, a scattering-regulated shroud for the equivalent electrically small object with the same complex shape is designed using the characteristic mode and discrete dipole approximation methods. Finally, the scattering manipulation layer was transformed into the original target. We also derived a theoretical formula for functional coatings that can be used to produce illusion performances for moderate or large complex-shaped targets. The feasibility and efficiency have been demonstrated by numerical simulations.

To investigate the damage patterns of AlGaAs/GaAs pHEMT transistors under High-Power Microwave (HPM) injection. A method for real-time monitoring of gain changes in AlGaAs/GaAs pHEMT chips at different injection powers has been proposed, which improves the accuracy of transistor damage threshold measurement. Subsequently, by fitting the damage threshold at different frequencies, it was found that the damage threshold of the device varied almost linearly in the high-frequency stage. This method has a certain value for studying the damage threshold of transistors under pulse action. Finally, AlGaAs/GaAs pHEMT chip was simulated using TCAD, and the dependence of the chip on different cap layer parameters was discussed.

This paper designs dual- and triple-band bandpass filters (BPFs) using half-mode substrate-integrated waveguide (HMSIW) resonators with slot-line perturbations. Subsequently, the resonance and coupling characteristics of the perturbed HMSIW resonators are analyzed. A dual-band BPF featuring the TE₁₀₀ and TE₁₀₂ modes, with independently tuned passbands, is realized through the incorporation of inner coupling slot lines and metal-hole rows to compensate for external coupling effects. Furthermore, input/output matching is achieved through the inset feedings of a quasi-coplanar waveguide, simultaneously exciting the desired modes. The total layout features a size of 0.725λg × 0.44λg. Building upon this dual-band BPF design, a novel triple-band BPF is realized by incorporating three additional slot lines to excite the higher mode (TE₁₀₃) for the third passband and control the second passband. Both BPFs are simulated, fabricated, and examined. Results reveal that the designed BPFs exhibit low insertion losses (<1.8dB), along with return losses better than 14dB. The adjacent passband isolation of both filters exceeds 20dB, and stopband high rejection is achieved by introducing more than three transmission zeros. Overall, the experimentally measured results demonstrate good agreement with the simulated ones.

A novel multi-resonant isolated three-port converter (NMI-TPC) for power decoupling. The NMI-TPC adopts a dual LC resonant structure (DLCRS) based on the three-active-bridge converter. By using the DLCRS, power decoupling between ports is achieved. The working principle of NMI-TPC is given. In order to improve the performance of the NMI-TPC, the effective value of the current (EVC) is optimized. By constructing the Lagrangian function, the problem of minimizing the EVC is solved. A prototype, operating at a power level of 1kW, has been developed to validate the theoretical framework.

The introduction of reactive power will increase the component stress and reduce the system transmission efficiency. To realize zero reactive power input, a two-coil wireless power transfer (WPT) system utilizing an adaptive tuning capacitor (ATC) is proposed. Compared with conventional switched-controlled capacitor, no additional information sampling is needed in proposed ATC. Simultaneously, proposed ATC has a wide impedance matching range, which expand its practicality greatly. With proposed ATC structure, any possible WPT system detuning occasions caused by control strategies, compensation network or component aging can be avoided automatically. the Finally, an experimental platform is built to verify the feasibility of proposed method.

Approximate computing is a promising approach to reduce power consumption in error-resilient applications with lax precision constraints. This paper presents an energy-efficient approximate multiplier with a novel imprecise 4-2 compressor based on incomplete-sorted circuits. The proposed approximate multiplier includes three parts: a most significant bit (MSB) compressed circuit, a middle-bit accumulation circuit, and a least significant bit (LSB) truncation circuit. First, we propose an ultra-low power approximate 4-2 compressor to improve efficiency, which is used for the middle-bit accumulation circuit. Then, since the weight and input distributions in neural networks usually follow a normal distribution, the MSB compressed circuit performs approximate computation on the accumulation of the significant bits. Finally, constant compensation in the LSB truncation circuits is utilized to balance accuracy and efficiency. Experimental results show that the 8-bit proposed design significantly improves the power-delay product (PDP) by 71.49% with satisfactory performance when compared with the traditional Dadda multiplier.