MIMO technology is effective to expand the aperture of radar arrays, which can improve the angular resolution. To ensure the consistency of the array amplitude and phase in the MIMO high-frequency-surface-wave-radar and guarantee the accuracy of orientation estimation in radar detection, we design and implement a MIMO HFSWR calibration source system based on asynchronous FIFO delayed retransmission, which overcomes traditional calibration limitations, such as the inability to calibrate transmitting and receiving arrays simultaneously and suboptimal calibration accuracy. Additionally, to resolve the problem that far-field HFSWR calibration must be conducted using drones or ships over the sea, we propose a near-field calibration method based on the designed calibration source system. This scheme enables the simultaneous calibration of the MIMO radar transmitting and receiving arrays in on-land near-field region. The results from the near-field calibration experiments indicate that when using multiple signal classification DOA estimation, RMSE of the angle estimation error is reduced to 0.7° after near-field calibration.

CMOS technology, commonly used in RFID circuits, faces limitations in power efficiency and chip size. This study optimizes the D Flip-Flop in RFID readers using Full Swing Gate Diffusion Input (FSGDI) with added buffers to reduce transistor count, power consumption, and delay, enhancing system performance. FSGDI achieves a stable output voltage and the lowest power consumption of 32.74 μW, reducing power by 84.91% with a lower delay of 0.15 ns and 3.3 V compared to CMOS. The D-flip-flop with FSGDI integration proposed in this study is beneficial for improving power efficiency and signal stability in RFID readers.

Micro-magnetometers with low-noise digital output are extensively utilized in both military and civilian applications. In this work, we propose a method that combines chopping modulation technology with interface ASIC design to effectively attenuate low-frequency 1/f noise. Magnetic shielding and chopping modulation are applied to tunneling magnetoresistance (TMR) sensors. The high-precision interface ASIC incorporates a ripple reduction circuit and utilizes a switched-capacitor sigma-delta topology. The ASIC chip for the TMR magnetometer was fabricated using a 0.35 μm CMOS process provided by Shanghai Huahong company. The active area of the interface ASIC is 3.2 mm × 3 mm. For testing, the interface chip, which includes a three-channel sigma-delta ADC, was integrated with the TMR sensor on the same PCB. The TMR sensor and ASIC operate with a total power consumption of 27 mW under a single 5 V power supply. The integrated TMR sensor system achieves a resolution of 260 pT/√Hz across the signal bandwidth, with a nonlinearity of 0.11% and an input range of ±100 μT.

This paper proposes a novel analog-to-digital converter (ADC) bandwidth doubler with Nyquist-rate sampling in analog-digital hybrid equivalent ideal filter (ADH-EIF). The ADH-EIF enables the required analog bandwidth of the sub-ADCs to be a half of the overall bandwidth of the frequency doubler by using analog mixers for wideband quadrature downconversion. In the bandwidth doubler the sample-and-hold (SH) circuits of the sub-ADCs in an ADH-EIF sample the down-converted signals at the peaks of the quadrature carriers at Nyquist rate. After that, zeros are inserted by upsampling in the digital domain. As a result, the output waveforms coincide with the ones of the oversampled signals in an ADH-EIF we reported previously. This means that the proposed doubler reduces the sampling rate at SH circuits by a factor of two. This reduction of the sampling rate is advantageous in mitigating the requirements for the sampling clocks on jitters. A circuit simulation shows a good fundamental signal transmission performance of the doubler for power spectral density and an eye pattern with a PAM4 signal.

The Wigner-Ville distribution (WVD) is a widely used time-frequency analysis (TFA) technique in non-stationary signal processing. However, as signal bandwidths increase, the low throughput of traditional serial architectures hinders real-time WVD processing. In this paper, we propose a novel dual-channel, fully parallel WVD architecture based on data shifting method. We comprehensively tap into the parallel potential in the WVD algorithm and present the corresponding data flow graph. By utilizing a symmetric dual-channel structure, we significantly streamline the generation and combination of autocorrelation sequences, while halving the total number of complex multiplications and FFTs. Additionally, we develop a memory-based, three-stage autocorrelation generator using a data-shifting technique, thereby obviating the necessity for address generation stages. Implementation results show that our design achieves a 95% latency reduction compared to the state-of-the-art WVD architectures, attaining a maximum clock frequency of 322 MHz on a Xilinx UltraScale+ FPGA. The proposed architecture holds substantial potential for augmenting the real-time processing of wide-band signals.

This paper proposes an extended technique to design broadband high-efficiency power amplifiers (PAs), in which the proposed extended design strategy integrates the theory of extended continuous mode PAs with an innovative approach for implementing circuits that meet the required theoretical impedances. The method uses impedance frequency modulation and is implemented by a two-stage branch line directional coupler with adjustable terminals. To illustrate the design procedure, a broadband high-efficiency PA operating in 0.7-3.0 GHz is designed and then fabricated by using a CGH40010F transistor. The test results show that the PA achieves an output power ranging from 40.1 to 42.8 dBm and a drain efficiency (DE) ranging from 60.8% to 75.0%. Additionally, the gain ranges from 10.1 to 12.5 dB within the target band. The realized PA exhibits an extremely competitive relative bandwidth of 124.3%.