This paper proposes a new type of embedded thermal pipe and thermal sheet (T-P&S) combined high power density PCB thermal structure for the problems of poor thermal conductivity and uneven thermal resistance distribution of the traditional PCB structure. A special thick copper thermal layer is constructed inside the traditional PCB, and low impedance thermal paths are established between the heat generating layer and the heat dissipation layer through the upper and lower thick-walled thermal pipes to realize a good heat exchange. Among them, the thermal conductivity layer and the signal layer are insulated to avoid thermoelectric coupling, which affects the electrical characteristics of the device. And with the traditional PCB heat dissipation structure for comparative experimental study, the experimental results show that, in the same thermal power, the designed PCB structure compared to the traditional PCB device surface temperature reduced by 5°C, synchronous reduction of 11%. Through the long-term application of thermal power experiments, it is concluded that the proposed structure HPD-PCB (T-P&S) can effectively and improve the uniformity of thermal stress distribution and reduce the steady-state thermal temperature of high-power devices.

Perovskite solar cells (PSCs) suffer output efficiency degradation during indoor low light operation (100 lux) due to dynamic internal resistance. This work proposes a constant voltage reference method (CV-RM) with dynamic impedance matching, enabling wide-illuminance Maximum Power Point Tracking (MPPT) via frequency-impedance co-regulation. Characterization establishes optimal voltage ratio K = 0.8. A digitally tuned oscillator adapts charge pump frequency (0.11-2.58 MHz) to match PSCs resistance. The all-analog design achieves MPP voltage locking, eliminating ADCs and digital processing. Experiments demonstrate: 100 lux cold start, full-range coverage (100-1000 lux), and cost reduction for billion-scale IoT deployments.

Spiking neural networks (SNNs) often face security and resource constraints, highlighting the need for lightweight hardware solutions. Tunneling field-effect transistors (TFETs) offer low-power operation for leaky integrate-and-fire (LIF) neurons due to their unique current mechanism. This work proposes a physical unclonable function (PUF) architecture based on TFET-LIF neurons for secure edge SNN applications. Leveraging random dopant fluctuation (RDF)-induced randomness in germanium-channel DG-TFETs as an entropy source, we emulate LIF behavior and analyze the impact of RDF, and work function variation (WFV). RDF is identified as the dominant factor influencing firing threshold (V_TH-LIF). A compact circuit is used to extract PUF responses, and every spike consumes 0.27 fJ. The PUF shows high reliability (≥ 97.11%), 49.8% uniqueness, and passes the NIST randomness test, enabling secure key generation and authentication.

In this paper, appearance, defects and electrical properties of 29-year-old PV modules in operation was studied. Almost all PV modules are visually intact, the appearance detects were mainly the peeling, blackening of the tin-coating strip and aging of aluminum alloy frames. The open circuit voltage (Voc) decreased slightly with annual degradation rate of 0.048%. The annual degradation rates of the short circuit (Isc), maximum power point voltage (Vmp), maximum power point circuit (Imp) were 0.38%, 0.91% and 0.93%, respectively. The power decreased significantly with annual degradation rate of 1.59%. The attenuation trend of power and (fill factor) FF is completely consistent.

Modern solid state drives (SSDs) based on NAND Flash Memory (NFM) have multi-level parallel resources to enhance their I/O performance. The page allocation policy, which is responsible for allocating logical pages to physical parallel resources, directly affects the efficiency of SSD parallelism utilization. Traditionally, the load-balancing page allocation policy relies on the number of commands rather than their actual latency. However, this policy fails to effectively balance the execution latency skew among the various parallel units of SSD, leading to parallelism loss. To address these problems, we propose a load-balancing method based on latency estimation called LEPA. Instead of relying on the number of commands, LEPA estimates the waiting latency of commands in pending to determine the load. Our experimental results indicate that our latency estimation-based load balancing page allocation significantly reduces the die load skew (by 85.9% on average) caused by the inaccurate estimations of traditional methods, with minimal overhead. Moreover, LEPA demonstrates an 8.0% improvement in plane-level parallelism. As a result, the proposed method effectively improves SSD system I/O performance and reduces request response time by 14.7%.

The single-transistor-clocked DET (STC-DET) effectively addresses the timing convergence issue in single-edge-triggered for high-frequency applications while reducing power consumption losses caused by redundant transitions. However, the introduction of the single-transistor-clocked buffer creates a more complex transistor stress distribution as well as a transmission network, and the low-power strategy based on a low supply voltage also makes the circuit more sensitive to threshold voltage degradation. This paper focuses on the STC-DET flip-flop as the research subject, employing transistor-level aging analysis to identify aging-sensitive transistors through de-aging analysis. A combination of transistor-level gate length tuning strategy and circuit structure optimization is applied for effective anti-aging design. Analysis results show that this optimization strategy significantly reduces the overall delay increase after aging under all corners. Notably, under the typical TT process corner, the 0→1 delay increase of the BOTTOM module is reduced by 58.2%, demonstrating the superiority of the proposed method.

This paper presents a 900-MHz low-power low-IF receiver for narrowband Ambient Internet of Things (A-IoT). To reduce the power consumption of the clock generation module, a free-running ring oscillator (RO) is employed. To mitigate the impact of RO initial frequency drift on sensitivity, a preamble-based frequency estimation (PBFE) algorithm is proposed. To suppress image interference, a passive mixer based on a Gm-C cell is implemented on-chip. Designed in 55-nm CMOS process, post-layout simulation results show that the proposed receiver achieves a link gain of 80-dB and a noise figure of 9.8-dB at 1-MHz IF. For a 90-kbps on-off keying (OOK) signal, the receiver demonstrates a sensitivity of -93-dBm and an image rejection ratio of 7.5-dB. The prototype operates at 1.2-V supply and consumes a total power of 580-μW. The model verification based on chip simulation results verifies that the PBFE algorithm improves sensitivity by 6-dB.